Contact us

A new window will open A new window will open

Research & Development Highlights

Our outstanding technologies will create the future. We are developing advanced memory technologies that are three to ten years ahead of the rest, and we are also adapting them to promote R&D of application and solution technologies for memory systems and storage systems.

Research & Development Field

New Memory Development

We are in the process of developing new memory technologies in order to widen our product portfolio and expand our business. We propose new memory cell technologies to realize even higher bit density file memories, as well as various high-speed nonvolatile memories. For example, we have demonstrated STT-MRAM technology(*1) and ReRAM technology(*2) with the highest density as of the time of publication(*3). As advanced device, process and circuit technologies need to achieve memories with new structures and new materials. We are challenging ourselves with new tasks on a daily basis.

*1 Spin Transfer Torque Random Access Memory
(We presented 4Gbit STT-MRAM technology at IEDM with SK-hynix in 2016.)

*2  Resistive Random Access Memory
(We presented 32Gbit ReRAM technology at ISSCC with SanDisk in 2013.)

*3 Figures according to our research.

Memory cell structures presented at the conference (Left: STT-MRAM; right: ReRAM)
Memory cell structures presented at the conference (Left: STT-MRAM; right: ReRAM)

TCAD (Technology CAD) Development

TCAD (technology CAD) is one of the key technologies for prospectively and effectively developing the leading-edge memory devices that require new materials and complex 3D structures.

To start, we establish fundamental models of process phenomena and device operations. We apply computational science such as first-principle calculation for a thorough understanding of electron-level or atomic-level microscopic phenomena.

Then, we promptly build the process and device models into our in-house TCAD system, which realizes robust simulation.

We make great contributions to good prospects and efficient advanced memory development not only by finding solutions to the technical issues with the memories currently under development but also by predicting the performance and possible issues of future generation memories before starting fabrication.

Development flow with TCAD
Development flow with TCAD

Next-Generation Lithography Process: Nanoimprint

In the optical lithography process, shorter wavelengths and higher NAs that increase the lens diameter have been introduced to meet demand for device miniaturization. As wavelength reduction and NA heightening are approaching their physical limitations, new techniques are emerging, such as multiple patterning that repeats optical lithography several times or EUVL (Extreme Ultra-Violet Lithography). However, due to the cost of process step increase and additional process tools, it is inevitable that process costs will increase.

In order to overcome the lithography process cost increase, we are developing nanoimprint lithography that can miniaturize devices at lower cost. The nanoimprint technique uses imprinting to transfer nanoscale patterns on a template to a Si wafer, and unlike conventional lithography tools, it does not require a lens optical system for reduction projection.

The nanoimprint is a highly anticipated next-generation lithography method to realize advanced memory devices with reduced cost.

Nanoimprint lithography
Nanoimprint lithography

Analytical Technologies for Next-Generation Devices

In order to achieve high-performance and high-functional next-generation memory devices, it is essentially required to have (1) device design and process technology for 3D nanostructures, (2) material technologies that can introduce various functional thin films, (3) analysis technology that can reveal device nanostructure and material composition.

As many 3D memory nanostructures consist of intricately stacked thin films, it is very important to accurately understand the nanostructures of individual films, the interfaces between them, and the elemental composition distribution in order to realize high-performance and high-reliability devices. New analytical techniques need to analyze nanometer-level 3D structures, and we are driving various advanced analysis methods to achieve this task.

Specifically, Atom Probe Tomography (APT) can reveal 3D elemental distribution by counting the atoms one by one, as shown in the left figure. The right figure is an example of transistor (MOSFET) elemental analysis that can successfully visualize the 3D profile of elements on the nanometer level.

The principle of the APT (left); an atom map of a transistor (right)
The principle of the APT (left); an atom map of a transistor (right)

HMB (Host Memory Buffer) technology for DRAM-less SSDs

Recently, laptop computers are becoming thinner and thinner, and built-in SSDs are required to be smaller in size, as well as lower in cost. But if the DRAM on an SSD is eliminated to reduce the number of SSD parts, it generally degrades the data read/write performance of the SSD.

We have successfully developed HMB (Host Memory Buffer) technology to realize a DRAM-less, high-performance, one-package SSD. HMB technology utilizes part of the host memory (DRAM) as if it were its own, and achieves equivalent performance to an SSD with DRAM.

As cooperation between the host driver and SSD is necessary, we developed HMB protocols for booting and connection, and standardized them in NVMe 1.2* with major CPU/OS vendors.

A DRAM-less, high-performance, one-package SSD with HMB technology is now a product of our SSD division, called BG series SSD. It is also one of our main consumer SSD products. We will continue to develop advanced technologies for high-performance, small, and low-cost SSDs.

* An interface specification for PCIe SSDs

Conventional SSD (left) and HMB-SSD (right): HMB-SSD utilizes a part of host DRAM instead of DRAM on SSD.

Conventional SSD (left) and HMB-SSD (right):
HMB-SSD utilizes a part of host DRAM instead of DRAM on SSD.

A Daisy-Chained Bridge Interface Technology for High-Bandwidth and Large-Capacity SSDs

As technologies such as AI rapidly evolve, SSDs increasingly require larger storage capacities and higher speed. In the near future, some applications will require SSDs with a capacity larger than 1 PB (1015 Bytes) and data bandwidth higher than 100 GB/s.

Power consumption at data centers is also increasing steadily, and if no countermeasures are taken, social issues might arise. Therefore, power reduction of SSDs used in data centers is also a very important task to accomplish.

We have managed to realize high circuit board density and high bandwidth simultaneously. In order to realize high density, we introduced the newly designed Bridge chip, which connects the SSD controller to a number of NAND flash memories via only a pair of two date wires in a daisy-chain* topology, one for downlink and the other for uplink. In addition, we have also introduced a novel signaling technology to taper the bandwidth at each stage of the daisy-chained bridge-chips for power reduction.

* A wiring method to connect multiple devices in series or in a ring

Our proposed daisy-chain based SSD interface (Data Downlink)
Our proposed daisy-chain based SSD interface (Data Downlink)

To Top
·Before creating and producing designs and using, customers must also refer to and comply with the latest versions of all relevant TOSHIBA information and the instructions for the application that Product will be used with or for.