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Research paper

  • 2019

2019 Conference Presentation and Publication List*

* All authors at submission are basically Toshiba Memory employees. Written in English.

Post Training Weight Compression with Distribution-based Filter-wise Quantization Step
  • S. Sasaki, et al.
  • IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings 8721356
Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application
  • S. Fujii, et al.
  • IEEE Symposium on VLSI Technology, Digest of Technical Papers, pp. TT189-TT190
Overview in Three-Dimensionally Arrayed Flash Memory Technology
  • R. Katsumata
  • IEEE Symposia on VLSI Technology and Circuits, Short Course 1
A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems
  • Y. Tsubouchi, et al.
  • IEEE Journal of Solid-State Circuits, 54(4),8613011, pp. 1086-1095
Live demonstration: FPGA-based CNN accelerator with filter-wise-optimized bit precision
  • K. Nakata, et al.
  • Proceedings - IEEE International Symposium on Circuits and Systems, 2019-May, 8702208
Circuit-size reduction for parallel chien search using minimal polynomial degree reduction
  • N. Kokubun, et al.
  • Proceedings - IEEE International Symposium on Circuits and Systems, 2019-May, 8702075
Grain-boundary-limited carrier mobility in polycrystalline silicon with negative temperature dependence: Modeling carrier conduction through grain-boundary traps based on trap-assisted tunneling
  • M. Hogyoku, et al.
  • Japanese Journal of Applied Physics, 58(SB), SBBA01
Comprehensive study of variability in poly-Si channel nanowire transistor
  • K. Ota, et al.
  • Japanese Journal of Applied Physics, 58(SB), SBBA06
Evaluation of electron traps in SiN x by discharge current transient spectroscopy: Verification of validity by comparing with conventional DLTS
  • H. Seki, et al.
  • Japanese Journal of Applied Physics, 58(SB), SBBK02
High mobility (>30 cm2 V-1 s-1) and low source/drain parasitic resistance In-Zn-O BEOL transistor with ultralow <10-20 A μm-1 off-state leakage current
  • N. Saito, et al.
  • Japanese Journal of Applied Physics, 58(SB), SBBJ07
Investigation of Switching-Induced Local Defects in Oxide-Based CBRAM Using Expanded Analytical Model of TDDB
  • R. Ichihara, et al.
  • IEEE Transactions on Electron Devices, 66(5), 8676360, pp. 2165-2171
A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems
  • T. Toi, et al.
  • Digest of Technical Papers - IEEE International Solid-State Circuits Conference, pp. 478 - 480
Device Challenges and Opportunities for ReRAM
  • K. Ota
  • IEEE International Reliability Physics Symposium, IRPS 2019 - Tutorial
3D Flash Memory - Electrical and Physical Characterizations for Memory Cell Reliability -
  • Y. Mitani
  • IEEE International Conference on Microelectronic Test Structures, ICMTS 2019 - Tutorial
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